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19-4822; Rev 0; 7/09
TION KIT EVALUA BLE ILA AVA
TMDS Digital Video Equalizer for HDMI/DVI Cables
Features
S Guaranteed Performance to 2.25Gbps (HDMI 1.3),
General Description
The MAX3815A cable equalizer automatically provides compensation for DVITM and HDMITM v1.3 cables. It extends the usable cable distance up to 40 meters (1.65Gbps) and 35 meters (2.25Gbps). The MAX3815A is designed to equalize signals encoded in the transitionminimized differential signaling (TMDS(R)) format. The MAX3815A features four CML-differential inputs and outputs (three data and one clock). It provides a loss-ofsignal (LOS) output that indicates loss-of-clock signal. The outputs include a disable function. Upon LOS, the chip is powered down. For direct chip-to-chip communication, the output drivers can be switched to one-half the DVI output specification to conserve power and reduce EMI. The output drive current can also be increased to allow the use of back termination resistors for improved signal integrity. Equalization can be automatic or set to manual control for specific in-cable applications. The MAX3815A is available in a 7mm x 7mm, 48-pin TQFP-EP package and operates over a 0C to +70C temperature range.
MAX3815A
Improved Jitter Performance at Low Source Amplitude, and Enhanced Output Driver 0 to 35 Meters Over HDMI Cable, 24 AWG 0 to 22 Meters Over HDMI Cable, 28 AWG 0 to 40 Meters Over HDMI Cable, 24 AWG 0 to 28 Meters Over HDMI Cable, 28 AWG
S Extends 2.25Gbps TMDS Interface Length
S Extends 1.65Gbps TMDS Interface Length
S Compatible with HDTV Resolutions 720p, 1080i,
1080p, and 1080p with 36-Bit Color
S Compatible with Computer Resolutions VGA,
SVGA, XGA, SXGA, UXGA, and WUXGA Required
S Fully Automatic Equalization, No System Control S 3.3V Power Supply S Power Dissipation of 0.6W (typ) S 7mm x 7mm, 48-Pin TQFP Lead-Free Package
Applications
Front-Projector HDMI/DVI Inputs High-Definition Televisions and Displays HDMI/DVI-D Cable-Extender Modules and Active Cable Assemblies LCD Computer Monitors HDMI 1.3 Deep Color Systems
PART MAX3815ACCM+
Ordering Information
TEMP RANGE 0NC to +70NC PIN-PACKAGE 48 TQFP-EP*
+Denotes a lead(Pb)-free/RoHS compliant package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet.
Typical Operating Circuits
HDMI OR DVI EXTENDER BOX
VIDEO SOURCE
UP TO 35m OF HDMI OR DVI CABLE
MAX3815A EQUALIZER
STANDARD LENGTH DVI-D OR HDMI CABLE
HDTV
MAX3816A DDC EXTENDER
Typical Operating Circuits continued at end of data sheet. DVI is a trademark of Digital Display Working Group. HDMI is a trademark of HDMI Licensing, LLC. TMDS is a registered trademark of Silicon Image Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range, VCC ................................-0.5V to +4.0V Voltage Range at Output CML Pins .....................-0.5V to +4.0V Voltage Range at Input CML Pins, RES, VCC_T, and GND_T ............................................ -0.5V to (VCC + 0.7V) Voltage Between Input CML Complementary Pair ........... 3.3V Voltage Between Output CML Complementary Pair ........ 1.4V Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 36.2mW/C above +70C) ........2896mW Operating Junction Temperature Range ......... -55C to +150C Storage Temperature Range............................ -55C to +150C Die Attach Temperature ..................................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.5V, TA = 0C to +70C. Typical Values are at VCC = +3.3V, external terminations = 50 1%, MAX3815A in automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25C, unless otherwise noted.) PARAMETER Power-Supply Current Supply-Noise Tolerance EQUALIZER PERFORMANCE Residual Output Jitter (Cables Only) 0.25Gbps to 1.65Gbps (Notes 1, 2, and 3) Residual Output Jitter (Cables Only) 1.65Gbps to 2.25Gbps (Notes 1, 2, and 3) CID Tolerance CONTROL AND STATUS CLKLOS Assert Level CML INPUTS (CABLE SIDE) Differential Input-Voltage Swing Common-Mode Input Voltage Input Resistance CML OUTPUTS (ASIC SIDE) 50W load, each side to VCC OUTLEVEL = HIGH OUTLEVEL = LOW 800 1000 500 910 VCC VCC 600 VCC 10 VCC 400 VCC + 10 mV mV mV 1200 mVP-P VID VCM RIN Single-ended At cable input 800 VCC 0.4 45 50 1000 1200 VCC + 0.1 55 mVP-P V W Differential peak-to-peak at EQ input with max 225MHz clock (see the Typical Operating Characteristics for more information) 50 mVP-P 1dB skin-effect loss at 825MHz 24dB skin-effect loss at 825MHz 1dB skin-effect loss at 825MHz 24dB skin-effect loss at 825MHz 20 0.05 UI 0.13 0.1 0.14 0.28 0.21 UI Bits SYMBOL ICC CONDITIONS Clock present (CLKLOS = HIGH) Clock and data absent (CLKLOS = LOW) DC to 500kHz MIN TYP 210 12 200 MAX 270 UNITS mA mVP-P
Differential Output-Voltage Swing
VOD
With back termination as shown in Figure 4, OUTLEVEL = OPEN Single-ended, OUTLEVEL = HIGH Single-ended, OUTLEVEL = HIGH Single-ended
Output-Voltage High Output-Voltage Low Output Voltage During Clock Absence (CLKLOS = LOW) 2
______________________________________________________________________________________
TMDS Digital Video Equalizer for HDMI/DVI Cables
ELECTRICAL CHARACTERISTICS
(VCC = +3.5V to +3.5V, TA = 0C to +70C. Typical Values are at VCC = +3.3V, external terminations = 50 1%, MAX3815A in automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25C, unless otherwise noted.) PARAMETER Common-Mode Output Voltage Rise/Fall Time (Note 1) LVTTL CONTROL AND STATUS INTERFACE LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input High Current LVTTL Input Low Current Open-Collector Output High Voltage Open-Collector Output Low Voltage Open-Collector Output Sink Current OUTLEVEL Input Open-State Current Tolerance 5 VIH VIL VIH(MIN) < VIN < VCC GND < VIN < VIL(MAX) RLOAD 10kW to VCC RLOAD 2kW to VCC 2.4 0.4 5 2.0 0.8 50 -100 V V A A V V mA A SYMBOL CONDITIONS 50W load, each side to VCC, OUTLEVEL = HIGH 20% to 80% 80 MIN TYP VCC 0.25 160 MAX UNITS V ps
MAX3815A
Note 1: AC specifications are guaranteed by design and characterization. Note 2: Cable input swing is 800mV to 1200mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak jitter, both deterministic plus random, as measured using an oscilloscope histogram with 5000 hits. Source jitter subtracted. Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros.
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
SUPPLY CURRENT vs. AMBIENT TEMPERATURE
240 230 SUPPLY CURRENT (mA) 220 200 190 180 170 160 150 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE (C) GAIN (dB) 210
Typical Operating Characteristics
INPUT RETURN LOSS vs. FREQUENCY
MAX3815A toc02
OUTLEVEL = OPEN, EQCONTROL = VCC, CLOCK SIGNAL ACTIVE
-5 -10 -15 -20 -25 -30
TMDS SOURCE DC-COUPLED TO MAX3815A INPUT (NOMINAL AMPLITUDE)
TMDS SOURCE AC-COUPLED TO MAX3815A
-35 -40 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
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MAX3815A toc02
250
0
3
TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
EQUALIZER INPUT AFTER 100ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc03
Typical Operating Characteristics (continued)
EQUALIZER INPUT EYE AFTER 100ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc04
DATA RATE = 2.25Gbps 30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz 20mV/div 350mV/div
DATA RATE = 2.25Gbps 30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz
500mV/div
5ns/div
100ps/div
EQUALIZER INPUT EYE AFTER 150ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc05
TOTAL JITTER vs. DATA RATE (50m HDMI CABLE)
200 180 160 TOTAL JITTER (psP-P) 140 120 100 80 60 40 20 0 250 750 0.1 0.2
MAX3815A toc06
DATA RATE = 742.5Mbps 24dB CABLE SKIN-EFFECT LOSS AT 370MHz
DVIGear SHRTM HDMI CABLE (22 AWG) PEAK-TO-PEAK JITTER IN PICOSECONDS
0.5 0.4 0.3 TOTAL JITTER (UIP-P)
350mV/div
PEAK-TO-PEAK JITTER IN UNIT INTERVALS
1250 DATA RATE (Mbps) 1750 2250
0
300ps/div
TOTAL JITTER vs. POWER-SUPPLY NOISE FREQUENCY (DATA RATE = 2.25Gbps)
170 TOTAL JITTER (psP-P) 160 150 140 130 120 110 100 1 10 100 FREQUENCY (kHz) 1000 10,000
NOISE AMPLITUDE: 200mVP-P DATA THROUGH 50m DVIGear SHR HDMI CABLE, 22 AWG
SHR is a trademark of DVIGear, Inc. 4 ______________________________________________________________________________________
MAX3815A toc07
180
TMDS Digital Video Equalizer for HDMI/DVI Cables
(Typical values are at VCC = +3.3V, TA = +25C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
TOTAL JITTER vs. CABLE LENGTH (CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG)
MAX3815A toc08
Typical Operating Characteristics (continued)
MAX3815A
DETERMINISTIC JITTER (UIP-P)
0.5 0.4 0.3 0.2 0.1 0 0 10
2.25Gbps 1.485Mbps 742.5Mbps NO EQ WITH MAX3815A EQ
120 TOTAL JITTER (psP-P) 110 100 90 80 70 60
50m OF DVIGear SHR HDMI CABLE WITH 35dB LOSS AT 1.11GHz
20 CABLE LENGTH (m)
30
40
50 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL AMPLITUDE (VP-P)
EQCONTROL VOLTAGE (RELATIVE TO VCC) vs. CABLE LENGTH (MANUAL EQ CONTROL)
0 -0.1 EQCONTROL VOLTAGE (V) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 10 20 30 CABLE LENGTH (m)
MAX3815A toc10
LOSS-OF-CLOCK ASSERT THRESHOLD vs. CABLE LENGTH
180 RESIDUAL JITTER (psP-P) 160 140 120 100 80 60 40 20 0 DIFFERENTIAL CLOCK AMPLITUDE (mVP-P) 300 250 200 150 100 50 0 0 6 12 18 24 30 36 CABLE LENGTH (m)
CABLE IS CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG WITH APPROXIMATELY 1.35dB OF LOSS PER METER AT 1.11GHz EQCONTROL VOLTAGE
CLOCK AMPLITUDE IS AT INPUT OF CABLE CABLE IS CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX, 28 AWG 225MHz CLOCK FREQUENCY
25MHz CLOCK FREQUENCY
RESIDUAL JITTER AT 2.25Gbps
EQUALIZER OUTPUT EYE AFTER 50m OF 22 AWG HDMI CABLE (DATA RATE = 2.25Gbps)
MAX3815A toc12
DVIGear SHR HDMI CABLE
200mV/div
100ps/div
_______________________________________________________________________________________
MAX3815A toc11
200
350
MAX3815A toc09
0.6
TOTAL JITTER vs. SIGNAL AMPLITUDE INPUT TO CABLE (DATA RATE 2.25Gbps)
130
5
TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
Pin Description
PIN 1, 4, 5, 8, 9, 12, 13, 16, 38 2 3 6 7 10 11 14 15 17 NAME VCC RX0_INRX0_IN+ RX1_INRX1_IN+ RX2_INRX2_IN+ RXC_IN+ RXC_INEQCONTROL FUNCTION Supply Voltage. All pins must be connected to VCC. Negative Data Input, CML Positive Data Input, CML Negative Data Input, CML Positive Data Input, CML Negative Data Input, CML Positive Data Input, CML Positive Clock Input, CML Negative Clock Input, CML Equalizer Control. This pin allows the user to control the equalization level of the MAX3815A. Connect the pin to GND for automatic operation. Set the voltage to VCC/2 for minimum equalization, or set the voltage between VCC - 1V to VCC for manual equalization. See the Applications Information section for more information. Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS clock from the cable. Connect pin to VCC through a 4.7k resistor. Not Connected. This pin is not internally connected. Ground Negative Clock Output, CML Positive Clock Output, CML Positive Data Output, CML Negative Data Output, CML Positive Data Output, CML Negative Data Output, CML Positive Data Output, CML Negative Data Output, CML Output-Level Control Input * HIGH: Standard swing (1000mVP-P) differential * OPEN: Standard swing (900mVP-P differential) with external 267 back termination resistor (see Figure 4) * LOW: One-half standard swing (500mVP-P differential) Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and sets a differential logic zero when forced high. Reserved. Must be connected to VCC for normal operation. Reserved. Must be connected to GND for normal operation. Reserved. Must be left open for normal operation. Exposed Pad. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation.
18 19 20, 23, 24, 25, 28, 29, 32, 33, 36, 37 21 22 26 27 30 31 34 35
CLKLOS N.C. GND RXC_OUTRXC_OUT+ RX2_OUT+ RX2_OUTRX1_OUT+ RX1_OUTRX0_OUT+ RX0_OUT-
39
OUTLEVEL
40 41, 43, 44 42 45-48 --
OUTON VCC_T GND_T RES EP
6
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TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
RX0_IN+/TERMINATED 3.3V CML INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX0_OUT+/-
RX1_IN+/-
TERMINATED 3.3V CML
INPUT BUFFER
ADAPTIVE EQ
LIMITING AMPLIFIER
DRIVER
RX1_OUT+/-
RX2_IN+/-
TERMINATED 3.3V CML
INPUT BUFFER
ADAPTIVE EQ
LIMITING AMPLIFIER
DRIVER
RX2_OUT+/-
EQCONTROL TERMINATED 3.3V CML INPUT BUFFER LIMITING AMPLIFIER DRIVER RXC_OUT+/-
RXC_IN+/-
CLKLOS
CLOCK LOS DETECTOR
OUTON MAX3815A OUTLEVEL
Figure 1. Functional Diagram
Detailed Description
The MAX3815A TMDS equalizer accepts differential CML input data at rates of 250Mbps up to 2.25Gbps (individual channel data rate). It automatically adjusts to skin-effect losses in copper cable. It consists of four CML input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting amplifiers, and four output buffers (Figure 1). The input buffers and the output drivers are implemented using current-mode logic (CML) (see Figures 4 and 5). The output drivers are open-collector and can be turned off with the OUTON pin. The OUTLEVEL pin sets the output drive current to one of three levels; see the Applications Information and Pin Description sections for more information. For details on interfacing with CML, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML.
The loss-of-clock signal detector indicates a loss-ofclock signal at the CLKLOS pin. This is an open-collector output that must be connected to VCC through a 4.7k external pullup. This resistor is required whether or not the LOS output is used. The three data channels each contain an independent adaptive equalizer. Each channel analyzes the incoming signal and determines the amount of equalization to apply. The limiting amplifier amplifies the signal from the adaptive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers.
Loss-of-Clock Signal Detector
Adaptive Equalizer
CML Input Buffers and Output Drivers
Limiting Amplifier
_______________________________________________________________________________________
7
TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
D0 D1 D2 D0 D1 D2
Applications Information
Typical shielded twisted pair (STP), unshielded twisted pair (UTP), and twin-ax cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a TMDS signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. The MAX3815A recovers the data and opens the signal eye through compensating equalization. The basic TMDS interface is composed of four differential serial links: three links carry serial data up to 2.25Gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 225MHz. TMDS, as with analog nVGA links, must handle a variety of resolutions and screen update rates. The actual range of digital serial rates is roughly 250Mbps to 2.25Gbps. For applications requiring ultra-high resolutions (e.g., QXGA), a "dual-link" DVI interface is used and is composed of six data links plus the clock, requiring two MAX3815A ICs with the clock going to both ICs. See Figure 2. The MAX3815A can be used to extend any TMDS interface as used under the following trademarked names: DVI (digital visual interface), DFPTM (digital flat-panel), PanelLink, ADCTM (Apple display connector), and HDMI (high-definition multimedia interface). A loss-of-clock signal is indicated by the CLKLOS output. A low level on CLKLOS indicates that the signal power on the RXC_IN pins has dropped below a threshold. When there is sufficient input voltage to the channel (typically greater than 100mVP-P differential), CLKLOS is high. The CLKLOS output is suitable for indicating problems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer. Note that the loss-of-clock circuitry is sensitive to a DC or AC voltage between the RXC_IN pins. A DC or AC voltage greater than Q30mV (typical) is sensed as an active clock signal.
MAX3815A
CLK
CLK
D3 D4 D5
MAX3815A
D3 D4 D5
Figure 2. Connection Scheme for MAX3815A in Dual Link Application
VCC
MAX3815A
TO CHIP POWERCONTROL CIRCUITRY
VCC 4.7k CLKLOS
Loss-of-Clock Signal (CLKLOS) Output
Figure 3. Simplified CLKLOS Output Circuit Schematic
+3.3V
MAX3815A
RX_OUT+ 50 50
267 HDM/DVI RECEIVER
RX_OUT-
12.5mA
Figure 4. Back Termination Circuit DFP is a trademark of Video Electronics Standards Association (VESA). ADC is a trademark of Apple Computer, Inc. 8 ______________________________________________________________________________________
TMDS Digital Video Equalizer for HDMI/DVI Cables
The loss-of-clock circuitry powers down the part whenever there is an absence of a clock signal. This mutes the output and reduces power consumption to 83mW whenever the input signal is removed. During powerdown, the MAX3815A's TMDS output pins go to a highimpedance state. The CLKLOS is an open-collector output that requires a resistive pullup to VCC for operation. The pullup resistor range is 1k to 10k (see Figure 3). The OUTLEVEL pin is a three-state input that allows the user to select between three output settings. Forcing this pin high results in the standard output signal level with no back terminations; leaving the pin open results in a standard output swing with 267 differential back termination resistors. Forcing this pin low results in one-half standard output signal level. Using back termination resistance improves signal integrity through absorption of reflections. It also shifts the single-ended output voltage high (VH) and low (VL). Table 1 shows the output voltages when using the MAX3815A in each of its three output configurations. The EQCONTROL pin allows the user to control the equalization in one of two ways: forcing the pin to ground sets the equalizer in automatic equalization mode, and forcing a voltage between VCC - 1V to VCC allows manual control of the equalization level. Set to VCC for maximum boost (long cable). Set to VCC - 1V for minimum boost (short cable).
Interface Models
MAX3815A
MAX3815A
VCC
50 RX_IN+/-
Output Level Control (OUTLEVEL) Input
Figure 5. Simplified Input Circuit Schematic
Using Back Termination
MAX3815A
TRANSIENT SUPRESSOR CLAMP
RX_OUT+
Equalizer Control (EQCONTROL) Input
RX_OUT-
PWRDWN 0
1 10mA OUTLEVEL = HIGH 12.5mA OUTLEVEL = OPEN 5mA OUTLEVEL = LOW
Figure 6. Simplified Output Circuit Schematic
Table 1. Output Settings and Swings
OUTLEVEL High Open Low BACK TERMINATION Open 267I Open DIFFERENTIAL SWING (mVP-P) 1000 910 500 SINGLE-ENDED HIGH (VH) VCC VCC - 85mV VCC SINGLE-ENDED LOW (VL) VCC - 500mV VCC - 540mV VCC - 250mV
_______________________________________________________________________________________
9
TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A
* The data and clock inputs should be wired directly between the cable connector and IC without stubs.
TYPICAL MAX3815A CABLE REACH (DATA RATE = 2.25Gbps)
60 50 CABLE LENGTH (m) 40 30 20 10 0 28 26 24 22 WIRE GAUGE (AWG)
* Place supply filter capacitors close to the MAX3815A inputs to provide a low inductance path for supply return currents. * Input and output data channel designations are only a guide. Polarity assignments can be swapped and channel paths can be interchanged. * An uninterrupted ground plane should be positioned beneath the high-speed I/Os. * Ground-path vias should be placed close to the input/ output connectors to allow a low inductance return current path. * Maintain 100 differential transmission line impedance into and out of the MAX3815A. * Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to Application Note 3854: MAX3815: Interfacing to the MAX3815 DVI/HDMI Cable Equalizer and the EV kit data sheet, MAX3815AEVKIT-HDMI. The exposed pad on the 48-pin TQFP-EP provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3815A and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information.
TYPICAL LIMIT OF CABLE WITH EQ AT 2.25Gbps
TYPICAL LIMIT OF CABLE WITHOUT EQ AT 2.25Gbps
Figure 7. Cable Reach
The OUTON pin is an LVTTL input. Force the pin low to enable the outputs. Force the pin high to set a differential zero on the outputs, irrespective of the signal at the inputs.
Output On (OUTON) Input
Exposed-Pad Package
TMDS performance is heavily dependent on cable quality. Deterministic jitter (DJ) can be caused by differential-tocommon-mode conversion (or vice versa) within a twisted pair (STP or UTP), usually a result of cable twist or dielectric imbalance. Refer to Application Note 3353: HFAN-04.5.4: `Jitter Happens' when a Twisted Pair is Unbalanced and Application Note 4218: Unbalanced Twisted Pairs Can Give You the Jitters! for more information. The data and clock inputs are the most critical paths for the MAX3815A and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3815A:
Cable Selection
Chip Information
PROCESS: SiGe BiPOLAR
Layout Considerations
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 48 TQFP-EP PACKAGE CODE C48E+8 DOCUMENT NO. 21-0065
10
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TMDS Digital Video Equalizer for HDMI/DVI Cables
Typical Operating Circuits (continued)
MAX3815A
VIDEO PROJECTOR
DVI-D INPUT
MAX3815A EQUALIZER
TMDS DESERIALIZER
DVI-D CABLE UP TO 35m OR 120ft (24 AWG STP)
SELECT
LAPTOP
VGA INPUT
RGB/HV ADC/SYNC
IMAGE SCALER AND PROCESSOR
PANEL INTERFACE TIMING AND DRIVERS
LCD, DLP, OR LCOS
Pin Configuration
GND_T VCC_T VCC_T VCC_T OUTON TOP VIEW RES RES RES RES OUTLEVEL
48 47 46 45 44 43 42 41 40 39 38 37 VCC 1 RX0_IN- 2 RX0_IN+ 3 VCC 4 VCC 5 RX1_IN- 6 RX1_IN+ 7 VCC 8 VCC 9 RX2_IN- 10 RX2_IN+ 11 VCC 12 13 14 15 16 17 18 19 20 21 22 23 24 RXC_IN+ RXC_INVCC VCC EQCONTROL CLKLOS GND RXC_OUTRXC_OUT+ GND GND N.C. *EP MAX3815A
+
GND 36 GND 35 RX0_OUT34 RX0_OUT+ 33 GND 32 GND 31 RX1_OUT30 RX1_OUT+ 29 GND 28 GND 27 RX2_OUT26 RX2_OUT+ 25 GND
*EXPOSED PAD.
TQFP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
VCC
11
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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